1. Field of the Invention
The present invention relates to a bumping process, more particularly to a bumping process capable of producing a bump having a planar surface.
2. Description of Related Art
Flip chip interconnect technology is a packaging technique for connecting a die to a circuit board. The process mainly includes forming a plurality of bumps on the respective contacts of the die and flipping the die over so that the bumps can connect with the respective bonding pads on the circuit board. In other words, the die is electrically connected to the circuit board via the bumps.
FIGS. 1A through 1C are schematic cross-sectional views showing the steps in a conventional method of forming bumps on the contacts of a die. First; as shown in FIG. 1A, a die 110 that has an active surface 112 and a plurality of contacts 114 disposed thereon is provided. Then, a protective layer 120 is formed on the active surface 112.
Next, as shown in FIG. 1B, a photolithographic/etching process is performed to form a plurality of openings 122 for exposing the respective contacts 114, located on protective layer 120. It should be noted that the protective layer 120 has a bulging portion P close to each opening 122 resulting from the opening 122 being slightly smaller than the contact 114. Then, an under-bump-metallurgy layer 150 is formed on the protective layer 120 and the contacts 114. After that, a photoresist layer 130 is formed on the under-bump-metallurgy layer 150. Next, a photolithographic/etching process is performed to form a plurality of openings 132 in the photoresist layer 130. The openings 132 expose the areas in the under-bump-metallurgy layer 150 that correspond to the contacts 114. Then, an electroplating process is performed to deposit gold inside the openings 132 so that a plurality of gold bumps is formed on the die 110. The gold bumps 140 are mechanically and electrically connected to their respective contacts through the under-bump-metallurgy layer 150.
As shown in FIG. 1C, the photoresist layer 130 is removed. Then, using the gold bumps 140 as a mask, the under-bump-metallurgy layer 150 not covered by the gold bumps 140 is removed to form a die structure 100 having a plurality of gold bumps 140 thereon. Because the area covered by the gold bump 140 includes a circular bulging portion P of the protective layer 120, the gold bump 140 also has a circular bulging portion Q corresponding to the circular bulging portion P of the protective layer 120.
FIG. 2 is a schematic cross-sectional view of a circuit board connected to a die through a bump fabricated using the conventional technique. In the conventional technique, the circuit board 200 is electrically connected to the die 110 through a single conductive direction bonding film 250 and prefabricated gold bumps 140. The single conductive direction bonding film 250 has a plurality of particles 252, each having a conductive inner core and an insulating outer layer, and the circuit board 200 has a plurality of bonding pads 210 thereon.
More specifically, when the circuit board 200 is electrically connected to the die 110 through the single conductive direction bonding film 250 and the gold bumps 140, some of the particles 252 will be compressed by the bulging portion Q of the gold bumps 140 and the bonding pads 210. Hence, the insulating outer layer of the particles 252 may break when the particles are subjected to compression between the bulging portion Q and the bonding pad 210 so that the inner conductive core of the particles are exposed. As a result, the conductive core of the particle 252 is electrically connected to the bulging portion Q and the bonding pad 210 through the broken outer insulating layer. Thus, an electrical connection between the die 110 and the circuit board 200 is formed.
It should be noted that the bulging portion Q of the gold bump 140 has a very small surface area. Therefore, when the gold bump 140 is electrically connected to the bonding pad 210 through the single conductive direction bonding film 250, the electrical connection has a lower reliability.